Микросхема LPC2366FBD100,551

Характеристики

LPC2366FBD100,551The LPC2366FBD100.551 is a 16-/32-bit Microcontroller based on ARM7TDMI-S core with RISC architecture operates at a maximum frequency of 72MHz. A 128-bit wide memory interface and an unique accelerator architecture enable 32-bit code execution at the maximum clock rate. For critical performance in interrupt service routines and DSP algorithms, this increases performance up to 30 % over Thumb mode. For critical code size applications, the alternative 16-bit Thumb mode reduces code by more than 30 % with minimal performance penalty. The device incorporates 256kB internal flash, 58kB internal RAM, 8-channel 10-bit A/D converter, 10-bit D/A converter, an Ethernet, four 32-bit timers and real-time clock (RTC) and 70 general-purpose I/O pins. This device also features peripherals like four UARTs, three inter-integrated circuit (I2C), one serial peripheral interface (SPI) modules and one integrated interchip sound (I2S).

• Dual Advanced high-performance bus (AHB) system
• Advanced vectored interrupt controller (VIC)
• General purpose DMA controller (GPDMA)
• Ethernet MAC with associated DMA controller
• USB 2.0 full-speed device with on-chip PHY and associated DMA controller
• CAN controller with two channels
• SD/MMC memory card interface
• 70 General purpose I/O pins with configurable pull-up/down resistors
• PWM/timer block with support for three-phase motor control
• Real-time clock (RTC) with separate power pin
• 2KB SRAM powered from the RTC power pin
• Watchdog timer (WDT)
• Standard ARM test/debug interface for compatibility with existing tools
• Emulation trace module supports real-time trace
• Four reduced power modes — Idle, sleep, power-down and deep power-down
• Processor wake-up from power-down mode via any interrupt able to operate during power-down mode
• Two independent power domains allow fine tuning of power consumption based on needed features
• Each peripheral has its own clock divider for further power saving
• Brownout detect with separate thresholds for interrupt and forced reset
• On-chip power-on reset